Glitch Power Minimization Techniques in Low Power VLSI Circuits
نویسندگان
چکیده
Due to miniaturization of circuits mobility degradation, velocity saturation and power dissipation issues are critical in the design of VLSI circuits. In this paper various techniques to minimize power dissipation due to glitches are discussed. Total power consumption consists of two major parts like static power consumption and dynamic power consumption. In the total power, the static power is 30% and dynamic power is 70 %. The power due to glitches is 70% of the dynamic power and 30 % of the total power. Various methods are developed by researchers to minimize the power due to glitches and some of them are presented here and comparison of various issues related to them is presented here.
منابع مشابه
Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit
Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in a...
متن کاملGlitch power minimization by selective gate freezing
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-Gates) that can be “frozen” by asserting a control signal. A frozen gate cannot propagate glitches to its output. Algorithms for gate selection and clustering that maximize the percentage of ...
متن کاملA Minimal-Cost Inherent-Feedback Approach for Low-Power MRF-Based Logic Gates
The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circui...
متن کاملA new low power high reliability flip-flop robust against process variations
Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...
متن کاملA Review on Glitch Reduction Techniques
This paper presents different techniques for reducing glitch power in digital circuits. The aim of this study is to minimize glitch power as glitch power comes under dynamic power, so that power dissipation will reduce up to some extent in digital circuits. Warren Shum et.al [2011] work shows glitch power in FPGA’s varies from 4 % to 73 % of total dynamic power having an average of 22.6 %. Warr...
متن کامل